1. Field of the Invention
The present invention relates to a power source voltage tracking circuit. In particular, it relates to a circuit which supplies stabilized voltage by tracking fluctuations in voltage.
2. Description of the Prior Art
A static random access memory (SRAM) device employs the art of precharging bit lines during readout operation, its bit lines swing within limits of voltage as much as 1 volt lower than the power source voltage by art.
Referring to FIG. 1, a load transistor T8, a diode-connected N channel MOS FET, is connected between a power source voltage Vcc and precharge line 20 to precharge the precharge line 20 with a voltage equal to Vcc-VTH (VTH is a threshold voltage of the load transistor T8).
Each pair of bit lines (BL1, BL1) (BLn, BLn) are connected with the precharge line 20 through an equalizing circuit 14 which comprises P-channel MOS FET transistors T1-T3 which are activated by equalizing pulse .phi.B and P channel MOS FET transistors T4, T5 which are in the normally ON state.
Between pairs of bit lines, a plurality of memory cells 10 are arranged in the form of matrices placed in rows and columns, and the memory cells in the same row are activated by row pulse .phi.WL. Each pair of the bit lines are connected to data lines DL, DL coupled with a sense amplifier 12 through pass transistors T6, T7 of P channel MOS FET. The pass transistors T6, T7 connected with each pair of the bit lines are activated by column pulses CD1 through CDn provided by a column decoder.
During a readout cycle, the pairs of bit lines (BL1, BL1) (BLn, BLn) are precharged and equalized with Vcc-VTH by a transistor T8 and equalizing circuit 14. Thereafter, data stored in memory cells 10 are sent to pairs of bit lines by a row pulse .phi.WL and the sent data is transmitted to a pair of data lines DL, DL through a pair of pass transistors activated by a column pulse, and amplified by a sense amplifier 12. The transistors T4, T5 are always turned on so as to prevent the pairs of bit lines from excessive voltage swings during the readout cycle of the memory cells 10. Such a precharging mechanism enables the sense amplifier to operate efficiently in terms of sensing time and amplification.
However, once power source voltage Vcc increases along with its fluctuations, the precharge voltage of the pairs of bit lines increase to the extent that power source voltage increased. Thereafter, if the power source voltage Vcc drops to normal power source voltage or below, the voltage precharged to the pairs of bit lines is maintained. Even if, practically, discharge takes place through memory cells connected between the pairs of bit lines, it takes a relatively long time to discharge to the precharge voltage which tracks fluctuations of the power source voltage. As a result, the voltage of pairs of data lines DL, DL during data readout operation is higher than power source voltage Vcc and sensing operation of the sense amplifier 12 is thereby disturbed.